1. Field of the Invention
This invention relates to semiconductor fabrication technologies, and more particularly, to a method of forming self-aligned silicide, also called salicide, in an integrated circuit (IC) without causing a bridging effect.
2. Description of Related Art
As semiconductor fabrication technologies advance to the submicron level of integration, the transistor elements in the integrated circuits, such as MOS (metal-oxide semiconductor) transistors, are formed with even smaller line widths. The downsizing of the polysilicon gates and wiring lines in MOS devices will then cause an increase in the resistance thereof. One solution to this problem is to form one or more metallization layers over the polysilicon gates and wiring lines and then convert these metallization layers into silicide through annealing. Since silicide has very good conductivity, it can help increase the conductivity of the polysilicon gates and wiring lines.
FIG. 1 is a schematic sectional diagram used to depict a conventional method for forming self-aligned silicide in a MOS IC device. As shown, the MOS IC device is constructed on a semiconductor substrate 100, such as a P-type substrate. A plurality of field oxide layers 102 are then formed in the substrate 100 to define the active regions (only one is shown in FIG. 1) where MOS transistors are to be formed. These field oxide layers 102 can be formed, for example, through a LOCOS (Local Oxidation of Silicon) process or an STI (Shallow Trench Isolation) process. The STI process is preferable since it allows the field oxide layers 102 to be sized more easily in fabrication and is more suitable for use in the fabrication of high-density IC devices with a submicron level of integration below 0.25 .mu.m (micrometer). Subsequently, conventional processes are performed to form a gate oxide layer 104 over the substrate 100 and then a polysilicon gate 106 over the gate oxide layer 104.
In the subsequent step, a pair of source/drain regions 118 are formed in the substrate 100 to define the channel region of the MOS transistor. Each of the source/drain regions 118 is composed of a lightly doped area 112 and a heavily doped area 117. The LDD (lightly doped drain) structure for the source/drain regions 118 can prevent a hot carrier effect due to a short channel. Moreover, a spacer structure 114 is formed from silicon oxide on the sidewall of the polysilicon gate 106.
In the subsequent step, a self-aligned silicide process is performed to form silicide layers 120, 122, respectively, over the polysilicon gate 106 and the source/drain regions 118 for the purpose of increasing the conductivity thereof. The self-aligned silicide process includes a first step of forming a metallization layer from a refractory metal over the substrate 100; a second step of performing a thermal annealing process on the wafer so as to allow the refractory metal to react with the silicon atoms in the polysilicon gate 106 and the source/drain regions 118 to thereby form silicide; and a third step of performing a wet etching process to remove selected portions of the silicide layer, with the remaining portions serving as the above-mentioned silicide layers 120, 122. After this, a dielectric layer 126 is formed over the entire top surface of the wafer; and then a contact window 128 is formed in the dielectric layer 126 to expose one of the silicide layers 122 formed over the source/drain regions 118. Next, a metal plug 130 is formed in the contact window 128.
One drawback to the foregoing self-aligned silicide process, however, is that the thermal annealing process can also cause the silicon atoms in the polysilicon gate 106 and the source/drain regions 118 to diffuse laterally, which can then cause formation of titanium siuicide layers 124a, 124b over the silicon oxide formed spacer structure 114. When a large amount of titanium silicide layer (for example the titanium silicide layer 124a on the left side of the polysilicon gate 106) forms, it can cause a bridging effect over the spacer structure 114, thus electrically interconnecting the polysilicon gate 106 and the source/drain regions 118. In other words, a short-circuit will occur between the polysilicon gate 106 and the source/drain regions 118, causing the resultant MOS transistor to be inoperable. Even though the titanium silicide layer (for example the titanium silicide layer 124b on the right side of the polysilicon gate 106) is not large enough to cause a bridging effect, it can nonetheless cause a short-circuit between the polysilicon gate 106 and the metal plug 130 formed in dielectric layer 126.
One conventional solution to the foregoing problem is depicted in the following with reference to FIGS. 2A-2B which are schematic sectional diagrams used to depict another conventional method for forming self-aligned silicide in a MOS IC device.
Referring first to FIG. 2A, the MOS IC device is constructed on a semiconductor substrate 200. A plurality of field oxide layers 202 are then formed at predefined locations over the substrate 200 to define the active regions (only one is shown) where MOS transistors are to be formed. Alter this, a gate oxide layer 204, a polysilicon gate 206, and a topping layer 210 are successively formed over the substrate 200 through conventional processes. Next. with the topping layer 210 serving as mask, a first ion-implantation process is performed on the wafer so as to dope an impurity element 216 of a low concentration into the unmasked portions of the wafer, thereby forming lightly doped areas 212 in the substrate 200. Further, a spacer structure 214 is formed on the sidewall of the stacked structure of the gate oxide layer 204, the polysilicon gate 206, and the topping layer 210. After this, with the spacer structure 214 serving as a mask, a second ion-implantation process is performed on the wafer so as to dope an impurity element into the polysilicon gate 206 to increase the conductivity thereof and also into the unmasked portions of the lightly doped areas 212 to form heavily doped areas 217. The heavily doped area 217 and the lightly doped area 212 in combination constitute a pair of source/drain regions 218 for the MOS transistor.
Referring next to FIG. 2B, in the subsequent step, the topping layer 210 is removed. Then, a self-aligned silicide process is performed to form silicide layers 220, 222, respectively, over the polysilicon gate 206 and the source/drain regions 218 for the purpose of increasing the conductivity thereof. This self-aligned silicide process includes a first step of forming a metallization layer from a refractory metal over the substrate 200; a second step of performing a thermal annealing process on the wafer so as to allow the refractory metal to react with the silicon atoms in the polysilicon gate 206 and the source/drain regions 218 to thereby form silicide; and a third step of performing a wet etching process to remove selected portions of the silicide layer, with the remaining portions serving as the above-mentioned silicide layers 220, 222. After this, a dielectric layer 226 is formed over the entire top surface of the wafer and then a contact window 228 is formed in the dielectric layer 226 to expose one of the silicide layers 222 formed over the source/drain regions 218. Next, a metal plug 230 is formed in the contact window 228.
The foregoing self-aligned silicide process differs from that utilized in the method of FIG. 1 particularly in that the etching process is controlled in such a manner that allows the topmost surface of the polysilicon gate 206 to be lower than the topmost point of the spacer structure 214. This can prevent the occurrence of a bridging effect over the spacer structure 214 that would electrically connect the polysilicon gate 106 to the source/drain region 218 due to lateral diffusion of silicon atoms from the polysilicon gate 206.
One drawback to the foregoing method, however, is that the same ion implantation process is used for the forming of the doped polysilicon gate 206 and the heavily doped areas 217 of the source/drain regions 218, thus requiring the impurity ions to be high enough in energy so as to be able to penetrate through the topping layer 210 into the polysilicon gate 206. However, higher energy ions would then cause the shallow junction 240 of the source/drain region 218 to be further increased in depth, easily causing a punch-through effect.
It seems that the foregoing problem can be solved simply by removing the topping layer 210 prior to the performing of the ion-implantation process. However, this is be unfeasible due to the fact that the topping layer 210 and the field oxide layers 202 are both formed from oxide so that the removal of the topping layer 210 through etching could also etch away a top part of the field oxide layers 202. This would cause the topmost side of the field oxide layers (as indicated by the reference numeral 202a in FIG. 2B) to be lower than the bottommost side of the source/drain regions 218. In the case that the contact window 228 is formed through a borderless contact method, as the case shown in FIG. 2B, the metal plug 230 easily comes through the void portion above the field oxide layer 202a and makes contact with substrate 200 at the part indicated by the reference numeral 250 in FIG. 2B, thereby resulting in a leakage current at the contact 250. Therefore, in order to prevent the occurrence of this leakage current, the contact window 228 should be formed precisely at the predefined location. However, this may not be easy to achieve.